NTU Mods is updated!

ModsEE4624

Device Parameter Extraction Layout Implementation

Current offering — AY2025/2026 Semester 2

This course aims to teach you the computer aided design of semiconductor devices and integrated circuits. In the first part, you will learn circuit simulation using the MOS transistor model and explore the impact of mask layout design on circuit performance. The process from simplified Boolean expression to actual circuit layout will be taught. In the second part, you will learn virtual device characterization using device simulator software to obtain the current-voltage characteristics of a MOS transistor. The third part is concerned with the extraction techniques of transistor parameters such as the threshold voltage.

AUs3.0 AUs
Grade Type
PrerequisiteEE3013
Not Available To Programme
Not Available To All Programme With
Not Available As BDE/UE To Programme
Not Available As Core To Programme
Not Available As PE To Programme
Mutually Exclusive With
Not Offered As BDE
Not Offered As Unrestricted Elective
Exam

Total hours per week: 6 hrs

Available Indexes

MonTueWedThuFri
1330

COMMON LEC (F61)

1330-1620 Tue

S1-B2B-13, S2-B5A-01

Wk1-6, Teaching Wk7-13

COMMON LEC (F61)

1330-1620 Tue

S1-B2B-13, S2-B5A-01

Wk1-6, Teaching Wk7-13

COMMON LEC (F62)

1330-1620 Thu

S1-B2B-13, S2-B5A-01

Wk1-6, Teaching Wk7-13

COMMON LEC (F62)

1330-1620 Thu

S1-B2B-13, S2-B5A-01

Wk1-6, Teaching Wk7-13

1400
1430
1500
1530
1600

Other Relevant Mods