Not offered in the current semester · Last offered AY2024/2025 Semester 2
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Grade Type | |
| Prerequisite | CE1005, CZ1005, CE1105, CZ1105 |
| Not Available To Programme | BCG, CEE 1, CSC, CSEC, EEE, EEE 1, EEEC, ENE 1, ENG, ME 1, ME(DES), ME(IMS), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Not Available To All Programme With | |
| Not Available As BDE/UE To Programme | |
| Not Available As Core To Programme | |
| Not Available As PE To Programme | |
| Mutually Exclusive With | SC2103 |
| Not Offered As BDE | Yes |
| Not Offered As Unrestricted Elective | |
| Exam |
Total hours per week: 8 hrs
Available Indexes
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
Other offerings
AY24/25
AY23/24
AY22/23
AY21/22
AY20/21
AY19/20
AY18/19
AY17/18
AY16/17
AY15/16
AY14/15