Historical snapshot — AY2018/2019 Semester 2 · View current offering →
ModsCE2003AY2018/2019 Semester 2
Digital Systems Design
AY2018/2019 Semester 2
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Categories | CoreMinorsBDE |
| Not Available To Programme | BCG, CE(2004-2010), CSC, CSEC, EEE, EEEC, ENG, ME(DES), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Mutually Exclusive With | CPE201 |
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| 1800 |