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AY2018/2019 Semester 2
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Categories | CoreMinorsBDE |
| Not Available To Programme | BCG, CE(2004-2010), CSC, CSEC, EEE, EEEC, ENG, ME(DES), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Mutually Exclusive With | CPE201 |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | |||||
|---|---|---|---|---|---|---|---|---|---|
| 830 | 10022 LAB (FE1) 0830-1030 Mon HWLAB3 Even Weeks | 10024 LAB (FEP1) 0830-1030 Tue HWLAB3 Even Weeks | |||||||
| 900 | |||||||||
| 930 | 10024 TUT (FEP1) 0930-1030 Thu TR+16 Wk2-13 | ||||||||
| 1000 | |||||||||
| 1030 | 10023 LAB (FE2) 1030-1230 Mon HWLAB3 Even Weeks | 10312 LAB (FE2) 1030-1230 Mon HWLAB3 Even Weeks | 10315 LAB (FE2) 1030-1230 Mon HWLAB3 Even Weeks | COMMON LEC (CE2) 1030-1130 Fri LT11 | |||||
| 1100 | |||||||||
| 1130 | |||||||||
| 1200 | |||||||||
| 1230 | 10023 TUT (FE2) 1230-1330 Thu TR+18 Wk2-13 | ||||||||
| 1300 | |||||||||
| 1330 | 10025 TUT (FEP2) 1330-1430 Thu TR+18 Wk2-13 | 10315 TUT (FEP2) 1330-1430 Thu TR+18 Wk2-13 | |||||||
| 1400 | |||||||||
| 1430 | 10025 LAB (FEP2) 1430-1630 Wed HWLAB3 Even Weeks | ||||||||
| 1500 | |||||||||
| 1530 | COMMON LEC (CE2) 1530-1630 Tue LT11 | 10022 TUT (FE1) 1530-1630 Fri TR+18 Wk2-13 | 10312 TUT (FE1) 1530-1630 Fri TR+18 Wk2-13 | ||||||
| 1600 | |||||||||
