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Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
Digital Systems Design
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| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
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| 1300 | |||||
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| 1800 |
| Mon | Tue | Wed | Thu | Fri | |||
|---|---|---|---|---|---|---|---|
| 930 | 10972 TUT (SCEB) 0930-1020 Thu TR+2, ONLINE Wk2,4-13, Teaching Wk3 | 10972 TUT (SCEB) 0930-1020 Thu TR+2, ONLINE Wk2,4-13, Teaching Wk3 | |||||
| 1000 | |||||||
| 1030 | COMMON LEC (SCL2) 1030-1120 Thu LT1, ONLINE Wk1,2,4-13, Teaching Wk3 | COMMON LEC (SCL2) 1030-1120 Thu LT1, ONLINE Wk1,2,4-13, Teaching Wk3 | |||||
| 1100 | |||||||
| 1130 | |||||||
| 1200 | |||||||
| 1230 | 10972 LAB (SCEB) 1230-1420 Thu HWLAB3 Odd Weeks | ||||||
| 1300 | |||||||
| 1330 | |||||||
| 1400 | |||||||
| 1430 | COMMON LEC (SCL2) 1430-1520 Tue LT1, ONLINE Wk1,2,4-13, Teaching Wk3 | COMMON LEC (SCL2) 1430-1520 Tue LT1, ONLINE Wk1,2,4-13, Teaching Wk3 | |||||
| 1500 | |||||||