ModsCE2003
Digital Systems Design
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Exam | 2 December 2024, 9.00 am - 11.00 am |
| Grade Type | N/A |
| Maintaining Dept | N/A |
| Prerequisites | or or CE1105 or |
| Mutually Exclusive With | SC2103 |
| Not Available To Programme | BCG, CEE 1, CSC, CSEC, EEE, EEE 1, EEEC, ENE 1, ENG, ME 1, ME(DES), ME(IMS), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Not Available To All Programme With | |
| Not available as Core for programmes | N/A |
| Not Available as PE for programmes | N/A |
| Not Available as BDE/UEs for programmes | N/A |
| Not Offered To | N/A |
Total hours per week: 0 hrs
Available Indexes
No indexes available for this semester
(This might be an old module not longer offered in AY24/25)