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AY2017/2018 Semester 1
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Categories | CoreMinorsBDE |
| Not Available To Programme | BCG, CE(2004-2010), CSC, CSEC, EEE, EEEC, ENG, ME(DES), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Mutually Exclusive With | CPE201 |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | ||
|---|---|---|---|---|---|---|
| 830 | 10035 LAB (SE1) 0830-1030 Wed HWLAB3 Even Weeks | 10036 LAB (SE2) 0830-1030 Wed HWLAB3 Odd Weeks | ||||
| 900 | ||||||
| 930 | ||||||
| 1000 | ||||||
| 1030 | ||||||
| 1100 | ||||||
| 1130 | 10035 TUT (SE1) 1130-1230 Thu TR+37 Wk2-13 | |||||
| 1200 | ||||||
| 1230 | ||||||
| 1300 | ||||||
| 1330 | 10036 TUT (SE2) 1330-1430 Fri TR+19 Wk2-13 | |||||
| 1400 | ||||||
| 1430 | COMMON LEC (CE2) 1430-1530 Tue LT10 | COMMON LEC (CE2) 1430-1530 Fri LT9 | ||||
| 1500 | ||||||
