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AY2019/2020 Semester 2
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Categories | CoreMinorsBDE |
| Not Available To Programme | BCG, CSC, CSEC, EEE, EEEC, ENG, ME(DES), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | ||||
|---|---|---|---|---|---|---|---|---|
| 930 | 10023 TUT (FEP1) 0930-1030 Thu LHN-TR+30 Wk2-13 | 10308 TUT (FEP1) 0930-1030 Thu LHN-TR+30 Wk2-13 | ||||||
| 1000 | ||||||||
| 1030 | COMMON LEC (CE2) 1030-1130 Fri LT11 | |||||||
| 1100 | ||||||||
| 1130 | ||||||||
| 1200 | ||||||||
| 1230 | 10307 LAB (FE3) 1230-1430 Tue HWLAB3 Odd Weeks | 10023 LAB (FEP1) 1230-1430 Wed HWLAB3 Even Weeks | ||||||
| 1300 | ||||||||
| 1330 | 10024 TUT (FEP2) 1330-1430 Thu LHN-TR+30 Wk2-13 | 10309 TUT (FEP2) 1330-1430 Thu LHN-TR+30 Wk2-13 | ||||||
| 1400 | ||||||||
| 1430 | 10024 LAB (FEP2) 1430-1630 Wed HWLAB3 Even Weeks | 10308 LAB (FE4) 1430-1630 Thu HWLAB3 Odd Weeks | 10309 LAB (FE5) 1430-1630 Thu HWLAB3 Even Weeks | 10310 LAB (FE5) 1430-1630 Thu HWLAB3 Even Weeks | ||||
| 1500 | ||||||||
| 1530 | COMMON LEC (CE2) 1530-1630 Tue LT11 | 10307 TUT (FE1) 1530-1630 Fri LHN-TR+15 Wk2-13 | 10310 TUT (FE1) 1530-1630 Fri LHN-TR+15 Wk2-13 | |||||
| 1600 | ||||||||
