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AY2022/2023 Semester 2
Review of Hardware Description Languages; Real-World Arithmetic; Control and Datapath design; Register Transfer Level (RTL) design in Verilog; Digital Design on FPGAs; Testbenches and Testing Strategies; Using design in registers, counters, shift registers, synchronous and asynchronous reset
| AUs | 3.0 AUs |
| Categories | CoreMinorsBDE |
| Not Available To Programme | BCG, CSC, CSEC, EEE, EEEC, ENG, ME(DES), ME(NULL), ME(RMS), MEEC(DES), MEEC(NULL), MEEC(RMS) |
| Mutually Exclusive With | SC2103 |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 830 | COMMON LEC (L1) 0830-0920 Mon LT20 | 10077 TUT (A29) 0830-0920 Tue TR+8 Wk2-13 | COMMON LEC (L1) 0830-0920 Wed LT20 | ||
| 900 | |||||
| 930 | |||||
| 1000 | |||||
| 1030 | 10077 LAB (A29) 1030-1220 Tue HPL_1 Even Weeks | ||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | 10076 LAB (A27) 1230-1420 Mon HPL_1 Even Weeks | ||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | 10076 TUT (A27) 1430-1520 Mon TR+9 Wk2-13 | ||||
| 1500 |
