Exam timetable data last updated 1 September 2026

Historical snapshot — AY2022/2023 Semester 2 · View current offering →
ModsSC2103AY2022/2023 Semester 2

Digital Systems Design

AY2022/2023 Semester 2

This course aims to develop skills in digital hardware design to meet basic industry expectations. Here, the principles established in CE1005/CZ1005/SC1005-Digital Logic will be extended to encompass circuits of greater complexity. These circuits are no longer implemented using multiple discrete logic elements, as presented in CE1005/CZ1005/SC1005, but rather use Application Specific Gate Array (ASIC) or Field Programmable Gate Array (FPGA) technologies. Both of these technologies can accommodate circuits of complexity equivalent to many millions of gates. This course will focus on FPGA technology as it is gaining commercial popularity (due to the cost of ASIC Implementations). The necessary logic and connectivity for both technologies is synthesised by software tools from code written in a Hardware Description Language. As such, this course presents you with circuit design techniques for more advanced systems in a methodical manner based on modern design techniques.

AUs3.0 AUs
CategoriesCoreMinorsBDE
Not Available To ProgrammeEEE, EEEC, ENG(EEE), ENG(ME), ENG(NULL), ME, ME(DES), ME(RMS), MEEC, MEEC(DES), MEEC(RMS)
Not Available To All Programme With(Admyr 2011-2020),
Mutually Exclusive WithCE2003, CE2103
Exam

Available Indexes

MonTueWedThuFri
830

COMMON LEC (L1)

0830-0920 Mon

LT20

10740 TUT (A29)

0830-0920 Tue

TR+8

Wk2-13

COMMON LEC (L1)

0830-0920 Wed

LT20

900
930
1000
1030

10740 LAB (A29)

1030-1220 Tue

HPL_1

Even Weeks

1100
1130
1200
1230

10739 LAB (A27)

1230-1420 Mon

HPL_1

Even Weeks

10741 LAB (A35)

1230-1420 Tue

HW3_1

Even Weeks

10743 TUT (Z57)

1230-1320 Fri

LHN-TR+19

Wk2-13

1300
1330
1400
1430

10739 TUT (A27)

1430-1520 Mon

TR+9

Wk2-13

10741 TUT (A35)

1430-1520 Tue

TR+37

Wk2-13

10743 LAB (Z57)

1430-1620 Fri

HW3_2

Even Weeks

1500
1530
1600