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AY2016/2017 Semester 1
The objective of this course is to introduce a hardware description language (HDL) for the specification, simulation, synthesis and implementation of digital logic systems. The students will have design practice sessions designing and implementing digital logic systems with commercial electronic design automation (EDA) tools. Digital Design using Hardware Description Language. Design Practice.
| AUs | 2.0 AUs |
| Categories | Core |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 1330 | COMMON LEC (F21) 1330-1630 Wed LHS-TR+33 | ||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 |
