Organization of H8S. Memory interfacing and timing diagram analysis. Exceptions and Associated Interface Considerations. Serial interface: asynchronous versus synchronous, I2C, SPI, IrDA, serial communication standards. Parallel I/O and Timers: Centronics interface, applications using timer modules, interface to display ICs. Direct Memory Access: Implicit/explicit transfers, organization of a DMA/DTC, transfer protocols. Timer and Mixed Signal Interface: the timer (TMR), timer-pulse (TPU) units, the programmable pulse generator (PPG), watchdog (WDG) timer, H8S ADC/DAC units interfacing techniques. Power Management: CPU operation modes; Expanded/Advanced mode of operations; Power-down modes of H8S; Various power-down modes supported); Transition between modes; Peripheral operations in various modes; Power consumption in different modes.
| AUs | 4.0 AUs |
| Grade Type | |
| Prerequisite | CPE201, CPE202, SC201, SC202 |
| Not Available To Programme | |
| Not Available To All Programme With | |
| Not Available As BDE/UE To Programme | BCE, BCG, CSC, EEE, ENG |
| Not Available As Core To Programme | |
| Not Available As PE To Programme | |
| Mutually Exclusive With | CE2007, M473, M473M, MP3006, SC206 |
| Not Offered As BDE | Yes |
| Not Offered As Unrestricted Elective | |
| Exam |
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