Advanced Computer Architecture
AY2022/2023 Semester 2
Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.
| AUs | 3.0 AUs |
| Categories | CoreBDE |
| Not Available To All Programme With | (Admyr 2011-2020) |
| Mutually Exclusive With | CE3001, CZ3001 |
| Exam |
Available Indexes
| Mon | Tue | Wed | Thu | Fri | ||
|---|---|---|---|---|---|---|
| 1230 | 10814 TUT (A25) 1230-1320 Mon TR+9 Wk2-13 | 10818 LAB (A35) 1230-1420 Tue HW1_1 Even Weeks | 10817 TUT (A33) 1230-1320 Tue TR+8 Wk2-13 | |||
| 1300 | ||||||
| 1330 | COMMON LEC (L1) 1330-1420 Mon LT2A | COMMON LEC (L1) 1330-1420 Wed LT1 | ||||
| 1400 | ||||||
| 1430 | 10814 LAB (A25) 1430-1620 Mon HW1_1 Even Weeks | 10817 LAB (A33) 1430-1620 Tue HW1_1 Even Weeks | 10818 TUT (A35) 1430-1520 Tue TR+21 Wk2-13 | |||
| 1500 | ||||||
| 1530 | ||||||
| 1600 | ||||||