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AY2018/2019 Semester 1
Digital Fundamentals. Digital Circuits; Combinational Logic Principles. Combinational Logic Circuits. Sequential Logic Principles. Sequential Logic Circuits. Memory, CPLDs, and FPGAs
| AUs | 4.0 AUs |
| Categories | Core |
| Mutually Exclusive With | EE2004 |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 930 | 36039 LAB (IL01) 0930-1230 Tue S2-B5C-07, S2-B4A-01 Wk9, Teaching Wk8,11 | 36039 LAB (IL01) 0930-1230 Tue S2-B5C-07, S2-B4A-01 Wk9, Teaching Wk8,11 | 36038 TUT (IT01) 0930-1130 Tue LHS-TR+31 | |||||||
| 1000 | ||||||||||
| 1030 | 36043 TUT (IT03) 1030-1230 Wed LHS-TR+31 | |||||||||
| 1100 | ||||||||||
| 1130 | ||||||||||
| 1200 | ||||||||||
| 1230 | ||||||||||
| 1300 | ||||||||||
| 1330 | 36038 LAB (IL02) 1330-1630 Thu S2-B4A-01, S2-B5C-07 Wk7,11, Teaching Wk10 | 36038 LAB (IL02) 1330-1630 Thu S2-B4A-01, S2-B5C-07 Wk7,11, Teaching Wk10 | 36043 LAB (IL04) 1330-1630 Thu S2-B5C-07., S2-B4A-01. Wk12, Teaching Wk6,10 | 36043 LAB (IL04) 1330-1630 Thu S2-B5C-07., S2-B4A-01. Wk12, Teaching Wk6,10 | ||||||
| 1400 | ||||||||||
| 1430 | 36039 TUT (IT02) 1430-1630 Fri LHS-TR+31 | |||||||||
| 1500 | ||||||||||
| 1530 | ||||||||||
| 1600 | ||||||||||
