Advanced MOS structures and process technology. Advanced bipolar transistors and process technology. MOS scaling rules and small geometry effects. CMOS latchup and isolation. Details: 1) MOS Structure. MOSFETS. NMOS Process. CMOS Process. P-Well CMOS. N-Well CMOS. Twin-Well CMOS. 2) Basic Bipolar Transistor Structures. Advanced Bipolar Transistor Structures. Introduction of BiCMOS. 3) Geometry Effect on Circuit Speed. Experimental Short-Channel Characteristics. Short-Channel Effect on Drain Current. Geometry Effects on Threshold Voltage. Hot Carrier Effect and Drain Engineering. Scaling Laws of MOS Devices. Velocity Saturation. 4) CMOS Latchup: Basic Switching Operation, Causes of Latchup, Latchup Characterization, and Latchup Prevention. 5) MOS Isolation. CMOS Isolation. New Isolation Techniques for CMOS.
| AUs | 3.0 AUs |
| Grade Type | |
| Prerequisite | EE3013 |
| Not Available To Programme | |
| Not Available To All Programme With | |
| Not Available As BDE/UE To Programme | |
| Not Available As Core To Programme | |
| Not Available As PE To Programme | |
| Mutually Exclusive With | |
| Not Offered As BDE | |
| Not Offered As Unrestricted Elective | |
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