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AY2016/2017 Semester 2
Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.
| AUs | 3.0 AUs |
| Categories | CoreBDE |
| Not Available To Programme | BCE, CE, CEEC |
| Not Available To All Programme With | (Admyr 2004-2010) |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | |||||
|---|---|---|---|---|---|---|---|---|---|
| 830 | 10282 LAB (FSP2) 0830-1030 Tue HWLAB2 Odd Weeks | ||||||||
| 900 | |||||||||
| 930 | COMMON LEC (CS3) 0930-1030 Mon LT2A | 10290 TUT (SSP3) 0930-1030 Thu TR+17 Wk2-13 | |||||||
| 1000 | |||||||||
| 1030 | 10284 LAB (SS1) 1030-1230 Mon HWLAB2 Even Weeks | 10286 LAB (SS3) 1030-1230 Mon HWLAB1 Odd Weeks | 10285 LAB (SS2) 1030-1230 Tue HWLAB2 Even Weeks | 10290 LAB (SSP3) 1030-1230 Tue HWLAB3 Odd Weeks | 10281 TUT (FSP1) 1030-1130 Tue TR+3 Wk2-13 | 10289 TUT (SSP2) 1030-1130 Wed TR+17 Wk2-13 | 10288 TUT (SSP1) 1030-1130 Thu TR+33 Wk2-13 | ||
| 1100 | |||||||||
| 1130 | 10286 TUT (SS3) 1130-1230 Tue TR+18 Wk2-13 | ||||||||
| 1200 | |||||||||
| 1230 | |||||||||
| 1300 | |||||||||
| 1330 | 10285 TUT (SS2) 1330-1430 Tue TR+16 Wk2-13 | 10287 TUT (SS4) 1330-1430 Wed TR+18 Wk2-13 | 10283 TUT (FSP3) 1330-1430 Fri TR+9 Wk2-13 | ||||||
| 1400 | |||||||||
| 1430 | 10281 LAB (FSP1) 1430-1630 Mon HWLAB2 Even Weeks | 10284 TUT (SS1) 1430-1530 Mon TR+31 Wk2-13 | 10289 LAB (SSP2) 1430-1630 Tue HWLAB3 Even Weeks | 10283 LAB (FSP3) 1430-1630 Wed HWLAB2 Odd Weeks | 10288 LAB (SSP1) 1430-1630 Wed HWLAB2 Even Weeks | 10287 LAB (SS4) 1430-1630 Thu HWLAB2 Even Weeks | COMMON LEC (CS3) 1430-1530 Fri LT2A | ||
| 1500 | |||||||||
| 1530 | |||||||||
| 1600 | |||||||||
| 1630 | 10282 TUT (FSP2) 1630-1730 Thu TR+15 Wk2-13 | ||||||||
| 1700 | |||||||||
