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Historical snapshot — AY2024/2025 Semester 1 · View current offering →
ModsCE3001AY2024/2025 Semester 1

Advanced Computer Architecture

AY2024/2025 Semester 1

Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.

AUs3.0 AUs
CategoriesCoreBDE
Not Available To ProgrammeBCG, CSC, CSEC
Not Available To All Programme With(Admyr 2021-onwards)
Mutually Exclusive WithCZ3001, SC3050
Exam

Available Indexes

MonTueWedThuFri
1030

10427 TUT (TEL1)

1030-1120 Wed

TR+15

Wk2-13

1100
1130
1200
1230

10429 LAB (TEL3)

1230-1420 Mon

HWLAB1

Odd Weeks

10428 LAB (TEL2)

1230-1420 Tue

HWLAB1

Odd Weeks

10431 LAB (TEL5)

1230-1420 Tue

HWLAB1

Even Weeks

10429 TUT (TEL3)

1230-1320 Thu

TR+7

Wk2-13

10427 LAB (TEL1)

1230-1420 Fri

HWLAB3

Even Weeks

1300
1330

10431 TUT (TEL5)

1330-1420 Thu

TR+8

Wk2-13

1400
1430

COMMON LEC (SCL3)

1430-1520 Mon

LT3

10430 LAB (TEL4)

1430-1620 Thu

HWLAB1

Even Weeks

1500
1530
1600
1630

10430 TUT (TEL4)

1630-1720 Wed

TR+9

Wk2-13

COMMON LEC (SCL3)

1630-1720 Fri

LT3

1700
1730

10428 TUT (TEL2)

1730-1820 Mon

TR+5

Wk2-13

1800