Advanced Computer Architecture
AY2023/2024 Semester 1
Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.
| AUs | 3.0 AUs |
| Categories | CoreBDE |
| Not Available To Programme | BCG, CSC, CSEC |
| Not Available To All Programme With | (Admyr 2021-onwards) |
| Mutually Exclusive With | CZ3001, SC3050 |
| Exam |
Available Indexes
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 1230 | 10466 LAB (BCGC) 1230-1420 Tue HWLAB1 Even Weeks | 10541 TUT (TEL3) 1230-1320 Thu LT11 Wk2-13 | |||
| 1300 | |||||
| 1330 | COMMON LEC (SCL3) 1330-1420 Mon LT11 | 10466 TUT (BCGC) 1330-1420 Thu LT11 Wk2-13 | |||
| 1400 | |||||
| 1430 | 10541 LAB (TEL3) 1430-1620 Mon HWLAB1 Odd Weeks | 10465 LAB (BCGB) 1430-1620 Thu HWLAB1 Even Weeks | |||
| 1500 | |||||
| 1530 | COMMON LEC (SCL3) 1530-1620 Fri LT15 | ||||
| 1600 | |||||
| 1630 | 10465 TUT (BCGB) 1630-1720 Wed TR+9 Wk2-13 | ||||
| 1700 |