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Historical snapshot — AY2022/2023 Semester 2 · View current offering →
ModsCE3001AY2022/2023 Semester 2

Advanced Computer Architecture

AY2022/2023 Semester 2

Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.

AUs3.0 AUs
CategoriesCoreBDE
Not Available To ProgrammeBCG, CSC, CSEC
Not Available To All Programme With(Admyr 2021-onwards)
Mutually Exclusive WithCZ3001, SC3050
Exam

Available Indexes

MonTueWedThuFri
830

10135 LAB (A24)

0830-1020 Mon

HW1_1

Wk3,5,7,9,11,13

900
930

10138 TUT (A30)

0930-1020 Tue

TR+9

Wk2-13

1000
1030

10138 LAB (A30)

1030-1220 Tue

HW1_1

Wk3,5,7,9,11,13

1100
1130

10135 TUT (A24)

1130-1220 Mon

LHN-TR+19

Wk2-13

1200
1230

10136 TUT (A25)

1230-1320 Mon

TR+9

Wk2-13

10140 LAB (A35)

1230-1420 Tue

HW1_1

Even Weeks

10139 TUT (A33)

1230-1320 Tue

TR+8

Wk2-13

1300
1330

COMMON LEC (L1)

1330-1420 Mon

LT2A

COMMON LEC (L1)

1330-1420 Wed

LT1

1400
1430

10136 LAB (A25)

1430-1620 Mon

HW1_1

Even Weeks

10139 LAB (A33)

1430-1620 Tue

HW1_1

Even Weeks

10140 TUT (A35)

1430-1520 Tue

TR+21

Wk2-13

1500
1530
1600