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Historical snapshot — AY2017/2018 Semester 2 · View current offering →
ModsCE3001AY2017/2018 Semester 2

Advanced Computer Architecture

AY2017/2018 Semester 2

Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.

AUs3.0 AUs
CategoriesCoreBDE
Not Available To ProgrammeBCG, CSC, CSEC
Exam

Available Indexes

MonTueWedThuFri
930

COMMON LEC (CE3)

0930-1030 Mon

LT4

1000
1030

10033 TUT (SE2)

1030-1130 Mon

TR+17

Wk2-13

10251 TUT (SE2)

1030-1130 Mon

TR+17

Wk2-13

10032 TUT (SE1)

1030-1130 Fri

TR+19

Wk2-13

10313 TUT (SE1)

1030-1130 Fri

TR+19

Wk2-13

1100
1130
1200
1230

10034 LAB (SEP1)

1230-1430 Wed

HWLAB1

Even Weeks

10251 LAB (SEP1)

1230-1430 Wed

HWLAB1

Even Weeks

10313 LAB (SEP1)

1230-1430 Wed

HWLAB1

Even Weeks

10032 LAB (SE1)

1230-1430 Fri

HWLAB2

Odd Weeks

10033 LAB (SE2)

1230-1430 Fri

HWLAB2

Even Weeks

1300
1330
1400
1430

10034 TUT (SEP1)

1430-1530 Wed

TR+17

Wk2-13

COMMON LEC (CE3)

1430-1530 Fri

LT4

1500