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Historical snapshot — AY2017/2018 Semester 1 · View current offering →
ModsCE3001AY2017/2018 Semester 1

Advanced Computer Architecture

AY2017/2018 Semester 1

Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.

AUs3.0 AUs
CategoriesCoreBDE
Not Available To ProgrammeBCG, CSC, CSEC
Exam

Available Indexes

MonTueWedThuFri
930

10049 TUT (BCG3)

0930-1030 Tue

TR+8

Wk2-13

1000
1030

10051 LAB (SEP1)

1030-1230 Tue

HWLAB3

Odd Weeks

10049 LAB (BCG3)

1030-1230 Fri

HWLAB2

Even Weeks

1100
1130

10050 TUT (SEA1)

1130-1230 Mon

TR+18

Wk2-13

1200
1230
1300
1330

10051 TUT (SEP1)

1330-1430 Fri

TR+7

Wk2-13

1400
1430

10050 LAB (SEA1)

1430-1630 Wed

HWLAB2

Even Weeks

1500
1530

COMMON LEC (CE3)

1530-1730 Mon

LT19

1600
1630
1700