Advanced Computer Architecture
AY2014/2015 Semester 2
Processor System Design: CPU interfaces, clock, control, data & address bus; System firmware. The CPU Architecture: including ISA, compiler relationship, control, pipelining, hazards, CISC/RISC/VLIW and issues of ILP. Memory Systems: cache, virtual memory systems and the MMU, access methods, reliability, error detection/correction. Performance Enhancements: superscalar; branching issues, multithreading, scalability, co-processors and enhancement units. Interfacing and Communications: I/O fundamentals, interrupts and interfacing, buses, protocols and arbitration. Computer Arithmetic: range, precision, real numbers, floating point and conversion, multi-precision arithmetic Multiprocessing: multiprocessing architectures and interconnections, shared memory and coherence, memory solutions Future directions: low power computing; testing, JTAG, system-on-chip and multi-core implementations, embedded systems issues, comparison of computational on CPU, DSP, FPGA and GPU.
| AUs | 3.0 AUs |
| Categories | CoreBDE |
| Not Available To Programme | BCG, CSC, CSEC |
| Exam |
Available Indexes
| Mon | Tue | Wed | Thu | Fri | |||||
|---|---|---|---|---|---|---|---|---|---|
| 930 | COMMON LEC (CE3) 0930-1030 Mon LT13 | ||||||||
| 1000 | |||||||||
| 1030 | 10131 LAB (SER1) 1030-1230 Wed HWLAB4 Even Weeks | 10524 LAB (SSR2) 1030-1230 Wed HWLAB4 Odd Weeks | 10529 LAB (SSR2) 1030-1230 Wed HWLAB4 Odd Weeks | ||||||
| 1100 | |||||||||
| 1130 | |||||||||
| 1200 | |||||||||
| 1230 | |||||||||
| 1300 | |||||||||
| 1330 | |||||||||
| 1400 | |||||||||
| 1430 | COMMON LEC (CE3) 1430-1530 Fri LT13 | ||||||||
| 1500 | |||||||||
| 1530 | |||||||||
| 1600 | |||||||||
| 1630 | |||||||||
| 1700 | |||||||||
| 1730 | 10131 TUT (SER1) 1730-1830 Tue LT13 Wk5-13 | 10524 TUT (SSR2) 1730-1830 Tue TR17 | 10529 TUT (SER1) 1730-1830 Tue LT13 Wk5-13 | ||||||
| 1800 | |||||||||