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AY2020/2021 Semester 1
VLSI System Architecture and Memory Management. Parallel Processing. High Speed Synchronous and Asynchronous design. System noise consideration. VLSI system verification and testability. System reliability.
| AUs | 3.0 AUs |
| Categories | Core |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | ||
|---|---|---|---|---|---|---|
| 1030 | COMMON LEC (EELE) 1030-1130 Mon LT15, LT28 Wk6-13, Teaching Wk1-5 | COMMON LEC (EELE) 1030-1130 Mon LT15, LT28 Wk6-13, Teaching Wk1-5 | COMMON LEC (EELE) 1030-1130 Thu LT7 | |||
| 1100 | ||||||
| 1130 | ||||||
| 1200 | ||||||
| 1230 | ||||||
| 1300 | ||||||
| 1330 | ||||||
| 1400 | ||||||
| 1430 | 34045 TUT (F21) 1430-1530 Thu TR+89 Wk2-13 | |||||
| 1500 | ||||||
