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AY2017/2018 Semester 1
VLSI System Architecture and Memory Management. Parallel Processing. High Speed Synchronous and Asynchronous design. System noise consideration. VLSI system verification and testability. System reliability.
| AUs | 3.0 AUs |
| Categories | Core |
| Mutually Exclusive With | E440N |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 1030 | COMMON LEC (LE) 1030-1130 Mon LT25 | COMMON LEC (LE) 1030-1130 Thu LT25 | |||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | 34043 TUT (F21) 1430-1530 Thu TR102 Wk2-13 | ||||
| 1500 |
