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AY2017/2018 Semester 2
Digital Fundamentals. Digital Circuits; Combinational Logic Principles. Combinational Logic Circuits. Sequential Logic Principles. Sequential Logic Circuits. Memory, CPLDs, and FPGAs.
| AUs | 4.0 AUs |
| Categories | Core |
| Mutually Exclusive With | IM1004 |
| Exam |
| Mon | Tue | Wed | Thu | Fri | |
|---|---|---|---|---|---|
| 930 | |||||
| 1000 | |||||
| 1030 | |||||
| 1100 | |||||
| 1130 | |||||
| 1200 | |||||
| 1230 | |||||
| 1300 | |||||
| 1330 | |||||
| 1400 | |||||
| 1430 | |||||
| 1500 | |||||
| 1530 | |||||
| 1600 | |||||
| 1630 | |||||
| 1700 | |||||
| 1730 | |||||
| 1800 |
| Mon | Tue | Wed | Thu | Fri | |||
|---|---|---|---|---|---|---|---|
| 930 | 32102 TUT (TD02) 0930-1130 Tue TR+67 | ||||||
| 1000 | |||||||
| 1030 | 32103 TUT (TD03) 1030-1230 Wed TR+67 | ||||||
| 1100 | |||||||
| 1130 | |||||||
| 1200 | |||||||
| 1230 | |||||||
| 1300 | |||||||
| 1330 | |||||||
| 1400 | |||||||
| 1430 | |||||||
| 1500 | |||||||
| 1530 | 32101 TUT (TD01) 1530-1730 Mon TR+67 | ||||||
| 1600 | |||||||
| 1630 | |||||||
| 1700 | |||||||
| 1730 | |||||||
| 1800 | |||||||
| 1830 | |||||||
| 1900 | 37621 TUT (PT11) 1900-2100 Mon TR+90 | 37622 TUT (PT12) 1900-2100 Mon TR+91 | 37623 TUT (PT13) 1900-2100 Fri TR+90 | 37624 TUT (PT14) 1900-2100 Fri TR+91 | |||
| 1930 | |||||||
| 2000 | |||||||
| 2030 | |||||||